The invention relates to an elementary logic circuit obtained by means of field effect transistors of gallium arsenide and is used in the manufacture of modules of high-speed integrated circuits having a low power consumption, consisting of gallium arsenide and compatible with the high-speed integrated circuits formed as logic circuits by the ECL 100 K technology on silicon.
The ECL 100 K technology (ECL is short for Emitter-Coupled-Logic) utilizing bipolar transistors permits obtaining high-speed integrated circuits. However, such circuits consume much energy. Therefore, attempts are being made to replace in certain cases the ECL 100 K technology by another technology, by which integrated circuits can be obtained, which operate at the same speed, but which consume much less energy.
However, one kind of logic circuits can be replaced only gradually by another kind of logic circuits. Consequently, it is necessary to replace in a first period a certain number of modules obtained according to the ECL 100 K technology by equivalent modules obtained according to the novel technology selected to this end. The two technologies thus have to coexist and it is absolutely necessary that they are made compatible. In these conditions, they must have:
the same supply voltage or voltages; PA1 the same control voltage level of the logic gates and PA1 the same form of transfer function of the logic gates.
When replacing a whole IC module obtained according to the ECL 100 K technology, this therefore first results in considering the possibility of replacing an elementary ECL 100 K gate by an equivalent gate obtained according to the novel technology.
An elementary gate according to the ECL technology is known, for example, from French Patent Specification Publication No. 2407612, published on May 25, 1979, in which such a gate is shown as a part of FIG. 1 and is in the form of a logic &lt;&lt;OR/NOR&gt;&gt; gate. It should be noted that in fact a &lt;&lt;NOR&gt;&gt; gate having a single input, rather having an inverter function, but capable of giving off two complementary signals is concerned. This gate is first constitued by a differential amplifier formed by two planar npn transistors T.sub.1 and T.sub.2 whose emitters are coupled and whose output is connected through a resistor R.sub.1 or R.sub.2 to a reference potential V.sub.CC. The base of the transistor T.sub.1 receives the input signal T.sub.1, while the base of the transistor T.sub.2 is connected to a reference potential V.sub.BB, which is an internal reference. In order to ensure that this differential stage is supplied with current, a transistor S.sub.1 is utilized, whose base is brought to a potential V.sub.B and whose emitter is connected through a resistor R.sub.1 to a third potential V.sub.EE.
The output of the differential stage constituted by the collector of the transistor T.sub.2 is connected to the base of another bipolar transistor T.sub.3, while the output constituted by the collector of the transistor T.sub.1 is connected to the base of another bipolar transistor T.sub.4. The collectors of the two transistors T.sub.3, T.sub.4 are applied to the supply potential V.sub.CC, while their emitters are supplied with current by a respective transistor S, which is connected in the same manner as the transistor S.sub.1. The output of the real signal is formed at the emitter of the transistor T.sub.3, while the output signal of its complementary transistor is formed at the emitter of the transistor T.sub.4.
The performance obtained by means of such a logic circuit is for each elementary gate a power consumption of the order of 20 mW, a propagation time of the order of 400 ps, a maximum operating frequency of the order of 1 GHz. The integration density can reach 1200 to 2000 gates per cm.sup.2.
The literature with respect to the consideration of novel high-speed low-consumption technologies has shown that the Schottky barrier field effect transistor of gallium arsenide constitutes a high-speed switching component, which can be monolithically integrated with resistors and Schottky diodes to form high-speed logic circuits or high-frequency circuits. This performance is due to the properties of gallium arsenide, which has a high electron mobility and a high saturation rate.
The invention relates to an elementary logic circuit obtained by means of Schottky barrier field effect transistors of gallium arsenide comprising a differential amplifier, whose first branch is constituted by the transistor T.sub.1 of the enhancement type controlled by the input signal E and connected through its drain, at which the output signal S.sub.1 is available, to a first supply voltage terminal (V.sub.DD) via the load resistor R.sub.1, whose second branch is constituted by the transistor T.sub.2 of the enhancement type controlled by a reference signal and connected through its drain, at which the output signal S.sub.2 is available, to the first supply voltage terminal (V.sub.DD) via the load resistor R.sub.2, the coupled sources of the transistors T.sub.1 and T.sub.2 being supplied with current by a transistor T.sub.5 of the charge depletion type connected in common shortcircuited gate/source arrangement to a second supply voltage terminal (V.sub.SS), while this circuit comprises secondly two paired stages designated as level translators, the first of which is constituted by a transistor T.sub.4 connected in common drain arrangement to the first supply voltage terminal (V.sub.DD) controlled by the output signal S.sub.1 of the first branch of the differential amplifier and connected by its source to the anode of a diode D.sub.4, and the second of which is constituted by a transistor T.sub.3 connected in common drain arrangement to the potential V.sub.DD, controlled by the output signal S.sub.2 of the second branch of the differential amplifier and connected by its source to the anode of a diode D.sub.3.
Such a logic gate is known from the prior art by the article of Katsuhiko Suyama et al, of Fujitsu Ltd., entitled "A GaAs high-speed counter using current mode logic" in "1983 IEEE Microwave and Millimeter wave monolithic Circuits Symposium", Boston, 31 May-1 June 1983, pages 12 to 16. This article describes a digital high-speed circuit of GaAs used for high-frequency applications. This circuit is obtained from an elementary logic gate according to the CML technology (CML is short for Current Mode Logic) shown in FIG. 2 of the aforementioned document. This logic gate is constituted by a differential amplifier and by two paired so-called buffer stages. The differential amplifier comprises two charge depletion field effect transistors normally connected in the forward direction and designated as DRIVER transistors, one of which is controlled by the input voltage (INPUT), while the other is controlled by a reference signal (REF). The coupled sources of these two transistors are connected to the drain of an enhancement field effect transistor which is normally pinched, whose gate and source, which are shortcircuited, are connected to the supply voltage V.sub.SS (-5 V), in a manner such that this transistor operates as a current source. The drains of the DRIVER transistors are connected to the supply voltage V.sub.DD =0 V (ground) through two load resistors R.sub.L. The voltage of these drains will control the respective gates of the enhancement field effect transistors of the BUFFER stages. The latter transistors are connected in common drain arrangement to the voltage V.sub.DD =0 and their source is connected to two series-connected diodes which are connected to a transistor constituting a current source analogous to that of the differential stage. The output signals of the logic gate are formed at the drains of the current source transistors of the BUFFERS in the form of an input signal amplified by one of these transistors and of its complementary signal for the other transistor.
This circuit operates by means of a single supply voltage V.sub.SS =-5 V, because the second supply voltage V.sub.DD =0 is ground and the third voltage REF is an internal reference. The supplementary supply voltage, which was designated by V.sub.B and which controlled the current source transistors in the description of the ECL cell according to the French Patent specification Publication No. 2407612, does not exist in the present circuit due to the fact that the gate of each of the three current source transistors is shortcircuited with the source and is brought to the potential V.sub.SS =-5 V.
Moreover, this circuit is completely compatible with the ECL logic circuit obtained on silicon.
However, the fact that this circuit utilizes for controlling the second transistor of the differential stage a reference signal REF involves certain drawbacks. The first drawback resides in the fact that this signal has to be formed on the same substrate as the circuit in the proximity of the latter, which reduces the integration density and increases the consumption of the circuit. However, the most important disadvantage is that the use of such a signal as a reference considerably reduces the dynamic range of the response of the elementary logic circuit. Other disadvantages not to be neglected reside in the use of charge depletion transistors in the level translater stages and in the realization of three current sources for the single elementary gate as well as in the use of two diodes per translator stage, which considerably increases the consumption of such a circuit.